1. Technical Field of the Invention
The present invention relates to a method for forming contact openings in an integrated circuit structure by plasma etching the insulating layer using a mixture of one or more fluorine containing gases and a nitrogenous gas. More particularly, the present invention relates to a high selectivity plasma etch process for preferentially etching insulating material with respect to a silicide, in an integrated circuit structure, using a mixture of a nitrogen containing gas and one or more fluorine containing etchant gases.
2. Description of the Related Art
With the increasing push of technology for higher density integrated circuits, low resistivity interconnection paths are critical to the fabrication of dense, high performance devices. In MOS devices, for example, one approach to reduced resistivity delay and increased switching speeds is the use of polycide and salicide structures, shown in FIGS. 1a and 1b.
Referring to FIG. 1a, a polycide structure 10 is a low resistivity multilayer structure that includes a refractory metal silicide 12 formed on a polysilicon layer 14 overlying a gate oxide 16 formed between source/drain regions 17 of a silicon gate MOSFET. Contact structures 20, 22 appear as vertical openings in insulation layer 24. The openings, when filled with a conducting material 26, such as aluminum or an aluminum alloy, electrically connect devices on one level of an integrated circuit.
Referring to FIG. 1b, a salicide or self-aligned gate structure 30 is often used to reduce sheet resistivity of shallow junctions of source/drain regions while simultaneously reducing the interconnect resistance of polysilicon lines. In this structure, a refractory metal silicide 32 is deposited both over polysilicon 34 and the underlying gate oxide 36 and between silicon dioxide spacers 38 which act as ion implantation masks for the source) drain regions 39. Contact structures 40, 42 appear as vertical openings formed in insulation layer 44. These openings may also be filled with metal 46 to electrically connect devices on one level of an integrated circuit.
Conventionally, contact openings are formed by etching through an insulation layer, such as oxide, nitride or oxynitride. These insulating layers typically overlay silicon of silicon-containing surfaces, e.g., single crystal silicon such as a silicon wafer, epitaxial silicon, polysilicon, or suicides such as titanium silicide in integrated circuit structures. To ensure formation of desired dimensions and profile for contact openings, the etchant must be highly selective to promote removal of the insulation layer and not the underlying layer, the top surface of which desirably defines the end of the contact, i.e., the "contact stop." Contact stop layers 25 (FIG. 1a), and 45 (FIG. 1b) are sometimes used to help define the lower boundary of a contact opening. These stop layers are commonly composed of metal alloys, such as titanium-tungsten.
To ensure complete removal of the thickest portion of the layer to be etched and to allow for the etchant to break through any slow etching layers, it is often necessary to plan some degree of "overetch" into the process. However, "punch through," whereby the etchant species fails to sufficiently select or discriminate between the insulation layer and the contact stop, can become a significant problem when overetching. As a result, the etch rate does not slow down upon reaching the underlying stop layer and, therefore, the stop layer may be left undesirably thin or even completely etched through. Such an attack by the etchant species alters the dimensions of the contact opening, the resistivity of the interconnection and, in a MOS device, the device switching speed.
FIG. 2 presents a SEM photograph of punch through of a titanium silicide layer following a CHF.sub.3 /CF.sub.4 etch through an oxide insulator. The low selectivity of this recipe to the titanium silicide renders this layered configuration ineffective in a MOS device. While such a low selectivity may be satisfactory for a highly planarized structure and for perfectly uniform etch/plasma chamber conditions, it is unacceptable in those applications where it is highly desirable to etch as little metal silicide as possible once such silicide is exposed during the etching of the overlying oxide. For example, it is desirable in some applications (e.g., MOS devices) to etch less than about 50 angstroms (5.times.10.sup.-3 .mu.m) of underlying silicide during the oxide etch.
Loss in device yield due to punch through may be accepted as an inevitable part of semiconductor fabrication. Alternatively, it may be desirable to supplement the thickness of the contact stop to compensate for punch through. For example, additional thickness may be added to a thinned titanium silicide layer by annealing an exposed silicon layer in the presence of titanium. Taking such a step not only detracts from fabrication throughput, but may also lead to variations in contact resistance in a device and across wafers and within a wafer lot. Hence, it would be advantageous to avoid such an annealing step.
U.S. Pat. No. 5,176,790, assigned to the assignee of the present invention, is directed to an improved process for etching vias through an insulation layer to provide multilevel inter-connection on an integrated circuit structure. Typically, vias are to be etched in a photoresist-masked silicon oxide layer that overlies an electrically conductive metal layer (such as aluminum, alloys or mixtures of aluminum/silicon and titanium/tungsten). In order to prevent deposition of organometallic residues or backsputtered metal in the via, the '790 patent proposes the addition of a nitrogen-containing gas (such as N.sub.2, NO, N.sub.2 H.sub.4) to the fluorocarbon etchant in a volume ratio of 1:15 to 1:2.
U.S. Pat. Nos. 5,254,213 and 5,269,879 also disclose the addition of a nitrogen-containing gas to fluorine-based etching chemistries used in the formation of vias between metal layers. In each case the nitrogenous gas passivates the electrically conducting metallic layers by forming nitrides which prevent sputtering or redeposition of the metallic layers onto the sidewalls of the vias.
While the above-referenced patents disclose improved etching processes and recipes for particular etch environments, it must be recognized that etching is a localized phenomenon. That is, selective etching depends on heterogeneous interactions of the gas phase species with the solid surface to be etched as well as minimal interactions at the underlying surfaces to avoid etching these underlying surfaces. As such, design and improvement of etching processes require careful consideration of many factors, including: the physical-chemical properties of the etchant under the selected process parameters,; the nature of the material to be etched; etch rate and selectivity of the etchant with respect to other materials subject to exposure to the etchant; and the ability of the etch mechanism to produce desired profiles. The precise effect of changing one or more parameters of a given etch process is neither well understood nor predictable. Hence, one of ordinary skill in the art will appreciate that what is known about specific etching processes may not be at all predictive of or applicable to what may be required in the formation of contact openings in insulating layer/silicide substrate layer configurations.
It would, therefore, be desirable to provide an insulating layer etch process which would exhibit high selectivity to silicides without any substantial reduction in the etch rate of the insulating material.